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mcm63p737k ? mcm63p819k 1 motorola fast sram advance information 128k x 36 and 256k x 18 bit pipelined burstram synchronous fast static ram the mcm63p737k and mcm63p819k are 4mbit synchronous fast static rams designed to provide a burstable, high performance, secondary cache. the mcm63p737k (organized as 128k words by 36 bits) and the mcm63p819k (organized as 256k words by 18 bits) integrate input registers, an output register, a 2bit address counter, and high speed sram onto a single monolithic circuit for reduced parts count in cache data ram applications. synchronous design allows precise cycle control with the use of an external clock (k). addresses (sa), data inputs (dqx), and all control signals except output enable (g ), sleep mode (zz), and linear burst order (lbo ) are clock (k) controlled through positiveedgetriggered noninverting registers. bursts can be initiated with either adsp or adsc input pins. subsequent burst addresses can be generated internally by the mcm63p737k and mcm63p819k (burst sequence operates in linear or interleaved mode dependent upon the state of lbo ) and controlled by the burst address advance (adv ) input pin. write cycles are internally selftimed and are initiated by the rising edge of the clock (k) input. this feature eliminates complex offchip write pulse generation and provides increased timing flexibility for incoming signals. synchronous byte write (sbx ), synchronous global write (sgw ), and synchro- nous write enable (sw ) are provided to allow writes to either individual bytes or to all bytes. the bytes are designated as aao, abo, etc. sba controls dqa, sbb controls dqb, etc. individual bytes are written if the selected byte writes sbx are asserted with sw . all bytes are written if either sgw is asserted or if all sbx and sw are asserted. for read cycles, pipelined srams output data is temporarily stored by an edgetriggered output register and then released to the output buffers at the next rising edge of clock (k). the mcm63p737k and mcm63p819k operate from a 3.3 v core power supply and all outputs operate on a 2.5 v or 3.3 v power supply. all inputs and outputs are jedec standard jesd85 compatible. ? mcm63p737k / mcm63p819k166 = 3.5 ns access / 6 ns cycle (166 mhz) mcm63p737k / mcm63p819k150 = 3.8 ns access / 6.7 ns cycle (150 mhz) mcm63p737k / mcm63p819k133 = 4 ns access / 7.5 ns cycle (133 mhz) ? 3.3 v +10%, 5% core power supply, 2.5 v or 3.3 v i/o supply ? adsp , adsc , and adv burst control pins ? selectable burst sequencing order (linear/interleaved) ? singlecycle deselect timing ? internally selftimed write cycle ? byte write and global write control ? sleep mode (zz) ? jedec standard 100pin tqfp and 119pin pbga packages this document contains information on a new product. specifications and information herein are subject to change without notice . order this document by mcm63p737k/d semiconductor technical data mcm63p737k mcm63p819k tq package tqfp case 983a01 zp package pbga case 99902 rev 1 1/24/00 ? motorola, inc. 2000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mcm63p737k ? mcm63p819k 2 motorola fast sram write register a write register b enable register burst counter adsp g clr write register c* write register d* sba sbb sbc * sbd * se3 15/16 17/18 sgw dataout register enable register k2 k address register 17/18 datain register 128k x 36 / 256k x 18 array se2 lbo adv k adsc sa sa1 sa0 sw se1 k 4/2 36/18 2 2 k2 dqa dqd/ dqadqb 36/18 functional block diagram zz * valid only for mcm63p737k. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mcm63p737k ? mcm63p819k 3 motorola fast sram v ss v ddq 37 38 34 35 36 42 43 39 40 41 45 46 44 31 32 33 50 49 48 47 94 93 97 96 95 89 88 92 91 90 86 85 87 100 99 98 81 82 83 84 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 dqb dqb dqb 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 dqb dqb v ddq v ss dqc dqc dqc v ss dqd dqd dqd dqd nc nc sa sa sa sa sa sa sa lbo nc nc v ddq v ss dqa dqa dqa dqb dqb dqb dqb dqa dqa v ss nc v dd zz dqa dqa dqa dqa v ss v ddq v ddq v ss dqc dqc dqc dqc v ddq v ss v ss v ddq dqd dqd dqc dqc nc v dd nc dqd dqd dqd v ss v ddq v dd v ss sbd sbc sbb sba se3 g se1 se2 sa sa sa sa sa sa sa sa sa1 sa0 v dd v ss k adv sw adsp adsc sgw 6 5 4 3 2 17 b c v ss g a d e f h j v ss v ss sbb v ss sa v ss v ss v ss sa sa sa sa sa sa sa sa nc sa sa nc nc nc dqb sa sa nc zz sw dqa dqa v ddq v ddq dqb v ddq dqb dqb dqa dqa nc v dd nc sa nc nc nc nc dqd dqd v ss sa0 nc lbo dqa dqa sa1 v ss dqd dqd v ddq dqd v ss nc dqa dqa sba sbd dqd dqd dqd dqd v ss kv ss dqc dqa v dd nc v dd nc v dd v ddq dqc v ss sgw dqb dqb dqb adv sbc dqc dqc v ddq dqc v ss g dqb se1 v ss dqc dqc dqc dqc v ss nc dqb v dd nc nc se2 sa adsc adsp k l m n p r t u v ddq v ddq se3 v ddq v ddq nc 119bump pbga top view not to scale 100pin tqfp top view mcm63p737k pin assignments f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mcm63p737k ? mcm63p819k 4 motorola fast sram mcm63p737k tqfp pin descriptions pin locations symbol type description 85 adsc input synchronous address status controller: active low, interrupts any ongoing burst and latches a new external address. used to initiate a read, write, or chip deselect. 84 adsp input synchronous address status processor: active low, interrupts any ongoing burst and latches a new external address. used to initiate a new read, write, or chip deselect (exception e chip deselect does not occur when adsp is asserted and se1 is high). 83 adv input synchronous address advance: increments address count in accordance with counter type selected (linear/interleaved). (a) 51, 52, 53, 56, 57, 58, 59, 62, 63 (b) 68, 69, 72, 73, 74, 75, 78, 79, 80 (c) 1, 2, 3, 6, 7, 8, 9, 12, 13 (d) 18, 19, 22, 23, 24, 25, 28, 29, 30 dqx i/o synchronous data i/o: axo refers to the byte being read or written (byte a, b, c, d). 86 g input asynchronous output enable input: low e enables output buffers (dqx pins). high e dqx pins are high impedance. 89 k input clock: this signal registers the address, data in, and all control signals except g , lbo , and zz. 31 lbo input linear burst order input: this pin must remain in steady state (this signal not registered or latched). it must be tied high or low. low e linear burst counter. high e interleaved burst counter. 32, 33, 34, 35, 44, 45, 46, 47, 48, 49, 50, 81, 82, 99, 100 sa input synchronous address inputs: these inputs are registered and must meet setup and hold times. 36, 37 sa1, sa0 input synchronous address inputs: these pins must be wired to the two lsbs of the address bus for proper burst operation. these inputs are registered and must meet setup and hold times. 93, 94, 95, 96 (a) (b) (c) (d) sbx input synchronous byte write inputs: axo refers to the byte being written (byte a, b, c, d). sgw overrides sbx . 98 se1 input synchronous chip enable: active low to enable chip. negated high e blocks adsp or deselects chip when adsc is asserted. 97 se2 input synchronous chip enable: active high for depth expansion. 92 se3 input synchronous chip enable: active low for depth expansion. 88 sgw input synchronous global write: this signal writes all bytes regardless of the status of the sbx and sw signals. if only byte write signals sbx are being used, tie this pin high. 87 sw input synchronous write: this signal writes only those bytes that have been selected using the byte write sbx pins. if only byte write signals sbx are being used, tie this pin low. 64 zz input sleep mode: this active high asynchronous signal places the ram into the lowest power mode. the zz pin disables the rams internal clock when placed in this mode. when zz is negated, the ram remains in low power mode until it is commanded to read or write. data integrity is maintained upon returning to normal operation. note: an internal pulldown is included for compatibility with sram devices that do not support sleep mode. a 100% pin compatibility can be achieved if zz is left open or pulled low. 15, 41, 65, 91 v dd supply core power supply. 4, 11, 20, 27, 54, 61, 70, 77 v ddq supply i/o power supply. 5, 10, 17, 21, 26, 40, 55, 60, 67, 71, 76, 90 v ss supply ground. 14, 16, 38, 39, 42, 43, 66 nc e no connection: there is no connection to the chip. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mcm63p737k ? mcm63p819k 5 motorola fast sram mcm63p737k pbga pin descriptions pin locations symbol type description 4b adsc input synchronous address status controller: active low, interrupts any ongoing burst and latches a new external address. used to initiate a read, write, or chip deselect. 4a adsp input synchronous address status processor: active low, interrupts any ongoing burst and latches a new external address. used to initiate a new read, write, or chip deselect (exception e chip deselect does not occur when adsp is asserted and se1 is high). 4g adv input synchronous address advance: increments address count in accordance with counter type selected (linear/interleaved). (a) 6k, 7k, 6l, 7l, 6m, 6n, 7n, 6p, 7p (b) 6d, 7d, 6e, 7e, 6f, 6g, 7g, 6h, 7h (c) 1d, 2d, 1e, 2e, 2f, 1g, 2g, 1h, 2h (d) 1k, 2k, 1l, 2l, 2m, 1n, 2n, 1p, 2p dqx i/o synchronous data i/o: axo refers to the byte being read or written (byte a, b, c, d). 4f g input asynchronous output enable input: low e enables output buffers (dqx pins). high e dqx pins are high impedance. 4k k input clock: this signal registers the address, data in, and all control signals except g , lbo , and zz. 3r lbo input linear burst order input: this pin must remain in steady state (this signal not registered or latched). it must be tied high or low. low e linear burst counter. high e interleaved burst counter. 2a, 3a, 5a, 6a, 3b, 5b, 2c, 3c, 5c, 6c, 2r, 6r, 3t, 4t, 5t sa input synchronous address inputs: these inputs are registered and must meet setup and hold times. 4n, 4p sa1, sa0 input synchronous address inputs: these pins must be wired to the two lsbs of the address bus for proper burst operation. these inputs are registered and must meet setup and hold times. 5l, 5g, 3g, 3l (a) (b) (c) (d) sbx input synchronous byte write inputs: axo refers to the byte being written (byte a, b, c, d). sgw overrides sbx . 4e se1 input synchronous chip enable: active low to enable chip. negated high e blocks adsp or deselects chip when adsc is asserted. 2b se2 input synchronous chip enable: active high for depth expansion. 6b se3 input synchronous chip enable: active low for depth expansion. 4h sgw input synchronous global write: this signal writes all bytes regardless of the status of the sbx and sw signals. if only byte write signals sbx are being used, tie this pin high. 4m sw input synchronous write: this signal writes only those bytes that have been selected using the byte write sbx pins. if only byte write signals sbx are being used, tie this pin low. 7t zz input sleep mode: this active high asynchronous signal places the ram into the lowest power mode. the zz pin disables the rams internal clock when placed in this mode. when zz is negated, the ram remains in low power mode until it is commanded to read or write. data integrity is maintained upon returning to normal operation. note: an internal pulldown is included for compatibility with sram devices that do not support sleep mode. a 100% pin compatibility can be achieved if zz is left open or pulled low. 4c, 2j, 4j, 6j, 4r v dd supply core power supply. 1a, 7a, 1f, 7f, 1j, 7j, 1m, 7m, 1u, 7u v ddq supply i/o power supply. 3d, 5d, 3e, 5e, 3f, 5f, 3h, 5h, 3k, 5k, 3m, 5m, 3n, 5n, 3p, 5p v ss supply ground. 1b, 7b, 1c, 7c, 4d, 3j, 5j, 4l, 1r, 5r, 7r, 1t, 2t, 6t, 2u, 3u, 4u, 5u, 6u nc e no connection: there is no connection to the chip. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mcm63p737k ? mcm63p819k 6 motorola fast sram v ss v ddq 37 38 34 35 36 42 43 39 40 41 45 46 44 31 32 33 50 49 48 47 94 93 97 96 95 89 88 92 91 90 86 85 87 100 99 98 81 82 83 84 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 sa nc nc 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 dqa dqa v ddq v ss nc nc nc v ss dqb dqb dqb nc nc nc sa sa sa sa sa sa sa lbo nc nc v ddq v ss nc nc nc nc dqa dqa dqa dqa dqa v ss nc v dd zz dqa dqa nc nc v ss v ddq v ddq v ss nc nc dqb dqb v ddq v ss v ss v ddq dqb dqb dqb dqb nc v dd nc nc nc nc v ss v ddq v dd v ss nc nc sbb sba se3 g se1 se2 sa sa sa sa sa sa sa sa sa1 sa0 v dd v ss k adv sw adsp adsc sgw 6 5 4 3 2 17 b c v ss g a d e f h j v ss v ss v ss v ss sa v ss v ss v ss sa sa sa sa sa sa sa sa sa sa sa sa nc nc nc sa sa nc zz sw nc nc v ddq v ddq nc v ddq dqa dqa dqa dqa nc v dd nc nc nc nc nc nc nc dqb v ss sa0 nc lbo nc dqa sa1 v ss nc dqb v ddq dqb v ss nc nc dqa sba v ss nc dqb nc dqb v ss kv ss dqb nc v dd nc v dd nc v dd v ddq nc v ss sgw dqa dqa nc adv sbb dqb nc v ddq nc v ss g nc se1 v ss dqb nc dqb nc v ss nc dqa v dd nc nc se2 sa adsc adsp k l m n p r t u v ddq v ddq se3 v ddq v ddq nc 119bump pbga top view not to scale 100pin tqfp top view mcm63p818 pin assignments f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mcm63p737k ? mcm63p819k 7 motorola fast sram mcm63p819k tqfp pin descriptions pin locations symbol type description 85 adsc input synchronous address status controller: active low, interrupts any ongoing burst and latches a new external address. used to initiate a read, write, or chip deselect. 84 adsp input synchronous address status processor: active low, interrupts any ongoing burst and latches a new external address. used to initiate a new read, write, or chip deselect (exception e chip deselect does not occur when adsp is asserted and se1 is high). 83 adv input synchronous address advance: increments address count in accordance with counter type selected (linear/interleaved). (a) 58, 59, 62, 63, 68, 69, 72, 73, 74 (b) 8, 9, 12, 13, 18, 19, 22, 23, 24 dqx i/o synchronous data i/o: axo refers to the byte being read or written (byte a, b). 86 g input asynchronous output enable input: low e enables output buffers (dqx pins). high e dqx pins are high impedance. 89 k input clock: this signal registers the address, data in, and all control signals except g , lbo , and zz. 31 lbo input linear burst order input: this pin must remain in steady state (this signal not registered or latched). it must be tied high or low. low e linear burst counter. high e interleaved burst counter. 32, 33, 34, 35, 44, 45, 46, 47, 48, 49, 50, 80, 81, 82, 99, 100 sa input synchronous address inputs: these inputs are registered and must meet setup and hold times. 36, 37 sa1, sa0 input synchronous address inputs: these pins must be wired to the two lsbs of the address bus for proper burst operation. these inputs are registered and must meet setup and hold times. 93, 94 (a) (b) sbx input synchronous byte write inputs: axo refers to the byte being written (byte a, b). sgw overrides sbx . 98 se1 input synchronous chip enable: active low to enable chip. negated high e blocks adsp or deselects chip when adsc is asserted. 97 se2 input synchronous chip enable: active high for depth expansion. 92 se3 input synchronous chip enable: active low for depth expansion. 88 sgw input synchronous global write: this signal writes all bytes regardless of the status of the sbx and sw signals. if only byte write signals sbx are being used, tie this pin high. 87 sw input synchronous write: this signal writes only those bytes that have been selected using the byte write sbx pins. if only byte write signals sbx are being used, tie this pin low. 64 zz input sleep mode: this active high asynchronous signal places the ram into the lowest power mode. the zz pin disables the rams internal clock when placed in this mode. when zz is negated, the ram remains in low power mode until it is commanded to read or write. data integrity is maintained upon returning to normal operation. note: an internal pulldown is included for compatibility with sram devices that do not support sleep mode. a 100% pin compatibility can be achieved if zz is left open or pulled low. 15, 41, 65, 91 v dd supply core power supply. 4, 11, 20, 27, 54, 61, 70, 77 v ddq supply i/o power supply. 5, 10, 17, 21, 26, 40, 55, 60, 67, 71, 76, 90 v ss supply ground. 1, 2, 3, 6, 7, 14, 16, 25, 28, 29, 30, 38, 39, 42, 43, 51, 52, 53, 56, 57, 66, 75, 78, 79, 95, 96 nc e no connection: there is no connection to the chip. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mcm63p737k ? mcm63p819k 8 motorola fast sram mcm63p819k pbga pin descriptions pin locations symbol type description 4b adsc input synchronous address status controller: active low, interrupts any ongoing burst and latches a new external address. used to initiate a read, write, or chip deselect. 4a adsp input synchronous address status processor: active low, interrupts any ongoing burst and latches a new external address. used to initiate a new read, write, or chip deselect (exception e chip deselect does not occur when adsp is asserted and se1 is high). 4g adv input synchronous address advance: increments address count in accordance with counter type selected (linear/interleaved). (a) 6d, 7e, 6f, 7g, 6h, 7k, 6l, 6n, 7p (b) 1d, 2e, 2g, 1h, 2k, 1l, 2m, 1n, 2p dqx i/o synchronous data i/o: axo refers to the byte being read or written (byte a, b). 4f g input asynchronous output enable input: low e enables output buffers (dqx pins). high e dqx pins are high impedance. 4k k input clock: this signal registers the address, data in, and all control signals except g , lbo , and zz. 3r lbo input linear burst order input: this pin must remain in steady state (this signal not registered or latched). it must be tied high or low. low e linear burst counter. high e interleaved burst counter. 2a, 3a, 5a, 6a, 3b, 5b, 2c, 3c, 5c, 6c, 2r, 6r, 2t, 3t, 5t, 6t sa input synchronous address inputs: these inputs are registered and must meet setup and hold times. 4n, 4p sa1, sa0 input synchronous address inputs: these pins must be wired to the two lsbs of the address bus for proper burst operation. these inputs are registered and must meet setup and hold times. 5l, 3g (a) (b) sbx input synchronous byte write inputs: axo refers to the byte being written (byte a, b). sgw overrides sbx . 4e se1 input synchronous chip enable: active low to enable chip. negated high e blocks adsp or deselects chip when adsc is asserted. 2b se2 input synchronous chip enable: active high for depth expansion. 6b se3 input synchronous chip enable: active low for depth expansion. 4h sgw input synchronous global write: this signal writes all bytes regardless of the status of the sbx and sw signals. if only byte write signals sbx are being used, tie this pin high. 4m sw input synchronous write: this signal writes only those bytes that have been selected using the byte write sbx pins. if only byte write signals sbx are being used, tie this pin low. 7t zz input sleep mode: this active high asynchronous signal places the ram into the lowest power mode. the zz pin disables the rams internal clock when placed in this mode. when zz is negated, the ram remains in low power mode until it is commanded to read or write. data integrity is maintained upon returning to normal operation. note: an internal pulldown is included for compatibility with sram devices that do not support sleep mode. a 100% pin compatibility can be achieved if zz is left open or pulled low. 4c, 2j, 4j, 6j, 4r v dd supply core power supply. 1a, 7a, 1f, 7f, 1j, 7j, 1m, 7m, 1u, 7u v ddq supply i/o power supply. 3d, 5d, 3e, 5e, 3f, 5f, 5g, 3h, 5h, 3k, 5k, 3l, 3m, 5m, 3n, 5n, 3p, 5p v ss supply ground. 1b, 7b, 1c, 7c, 2d, 4d, 7d, 1e, 6e, 2f, 1g, 6g, 2h, 7h, 3j, 5j, 1k, 6k, 2l, 4l, 7l, 6m, 2n, 7n, 1p, 6p, 1r, 5r, 7r, 1t, 4t, 2u, 3u, 4u, 5u, 6u nc e no connection: there is no connection to the chip. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mcm63p737k ? mcm63p819k 9 motorola fast sram truth table (see notes 1 through 5) next cycle address used se1 se2 se3 adsp adsc adv g 3 dqx write 2, 4 deselect none 1 x x x 0 x x highz x deselect none 0 x 1 0 x x x highz x deselect none 0 0 x 0 x x x highz x deselect none x x 1 1 0 x x highz x deselect none x 0 x 1 0 x x highz x begin read external 0 1 0 0 x x x highz x begin read external 0 1 0 1 0 x x highz read continue read next x x x 1 1 0 1 highz read continue read next x x x 1 1 0 0 dq read continue read next 1 x x x 1 0 1 highz read continue read next 1 x x x 1 0 0 dq read suspend read current x x x 1 1 1 1 highz read suspend read current x x x 1 1 1 0 dq read suspend read current 1 x x x 1 1 1 highz read suspend read current 1 x x x 1 1 0 dq read begin write external 0 1 0 1 0 x x highz write continue write next x x x 1 1 0 x highz write continue write next 1 x x x 1 0 x highz write suspend write current x x x 1 1 1 x highz write suspend write current 1 x x x 1 1 x highz write notes: 1. x = don't care. 1 = logic high. 0 = logic low. 2. write is defined as either 1) any sbx and sw low or 2) sgw is low. 3. g is an asynchronous signal and is not sampled by the clock k. g drives the bus immediately (t glqx ) following g going low. 4. on write cycles that follow read cycles, g must be negated prior to the start of the write cycle to ensure proper write data setup times. g must also remain negated at the completion of the write cycle to ensure proper write data hold times. asynchronous truth table operation zz g i/o status read l l data out (dqx) read l h highz write l x highz deselected l x highz sleep h x highz linear burst address table (lbo = v ss ) 1st address (external) 2nd address (internal) 3rd address (internal) 4th address (internal) x . . . x00 x . . . x01 x . . . x10 x . . . x11 x . . . x01 x . . . x10 x . . . x11 x . . . x00 x . . . x10 x . . . x11 x . . . x00 x . . . x01 x . . . x11 x . . . x00 x . . . x01 x . . . x10 interleaved burst address table (lbo = v dd ) 1st address (external) 2nd address (internal) 3rd address (internal) 4th address (internal) x . . . x00 x . . . x01 x . . . x10 x . . . x11 x . . . x01 x . . . x00 x . . . x11 x . . . x10 x . . . x10 x . . . x11 x . . . x00 x . . . x01 x . . . x11 x . . . x10 x . . . x01 x . . . x00 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mcm63p737k ? mcm63p819k 10 motorola fast sram write truth table cycle type sgw sw sba sbb sbc (see note 1) sbd (see note 1) read h h x x x x read h l h h h h write byte a h l l h h h write byte b h l h l h h write byte c (see note 1) h l h h l h write byte d (see note 1) h l h h h l write all bytes h l l l l l write all bytes l x x x x x note: 1. valid only for mcm63p737k. absolute maximum ratings (see note 1) rating symbol value unit notes power supply voltage v dd v ss 0.5 to 4.6 v i/o supply voltage v ddq v ss 0.5 to v dd v input voltage relative to v ss for any pin except v dd v in , v out v ss 0.5 to v dd + 0.5 v input voltage (threestate i/o) v it v ss 0.5 to v ddq + 0.5 v output current (per i/o) i out 20 ma package power dissipation p d 1.6 w 2 temperature under bias t bias 10 to 85 c storage temperature t stg 55 to 125 c notes: 1. permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to recommended oper- ating conditions. exposure to higher than recommended voltages for extended periods of time could affect device reliability. 2. power dissipation capability is dependent upon package characteristics and use environment. see package thermal characteristics. package thermal characteristics rating symbol max unit notes tqfp junction to ambient (@ 200 lfm) singlelayer board fourlayer board r q ja 40 25 c/w 1, 2 junction to board (bottom) r q jb 17 c/w 3 junction to case (top) r q jc 9 c/w 4 pbga junction to ambient (@ 200 lfm) singlelayer board fourlayer board r q ja 38 22 c/w 1, 2 junction to board (bottom) r q jb 14 c/w 3 junction to case (top) r q jc 5 c/w 4 notes: 1. junction temperature is a function of onchip power dissipation, package thermal resistance, mounting site (board) temperatur e, ambient temperature, air flow, board population, and board thermal resistance. 2. per semi g3887. 3. indicates the average thermal resistance between the die and the printed circuit board. 4. indicates the average thermal resistance between the die and the case top surface via the cold plate method (mil spec883 met hod 1012.1). this device contains circuitry to protect the inputs against damage due to high static volt- ages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maxi- mum rated voltages to this highimpedance circuit. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mcm63p737k ? mcm63p819k 11 motorola fast sram dc operating conditions and characteristics (v dd = 3.3 v +10%, 5%, t a = 0 to 70 c, unless otherwise noted) recommended operating conditions and dc characteristics (voltages referenced to v ss = 0 v) parameter symbol min typ max unit 2.5 v i/o supply supply voltage v dd 3.135 3.3 3.465 v i/o supply voltage v ddq 2.375 2.5 2.9 v input low voltage v il 0.3* e 0.7 v input high voltage v ih 1.7 e v dd + 0.3** v input high voltage i/o pins v ih2 1.7 e v ddq + 0.3** v output low voltage (i ol = 2 ma) v ol e e 0.7 v output high voltage (i oh = 2 ma) v oh 1.7 e e v 3.3 v i/o supply supply voltage v dd 3.135 3.3 3.465 v i/o supply voltage v ddq 3.135 3.3 v dd v input low voltage v il 0.5* e 0.8 v input high voltage v ih 2 e v dd + 0.5*** v input high voltage i/o pins v ih2 2 e v ddq + 0.5*** v output low voltage (i ol = 8 ma) v ol e e 0.4 v output high voltage (i oh = 4 ma) v oh 2.4 e e v * undershoot: v il > 1.0 v for t < 20% t khkh . ** overshoot: v ih /v ih2 < v dd /v ddq + 1.0 v (not to exceed 3.6 v) for t < 20% t khkh . *** overshoot: v ih /v ih2 < v dd /v ddq + 1.0 v (not to exceed 4.6 v) for t < 20% t khkh . supply currents parameter symbol min typ max unit notes input leakage current (0 v v in v dd ) i lkg(i) e e 1 m a 1 output leakage current (0 v v in v ddq ) i lkg(o) e e 1 m a ac supply current (device selected, mcm63p737k / 819k166 all outputs open, freq = max) mcm63p737k / 819k150 includes v dd only mcm63p737k / 819k133 i dda e e 500/430 470/400 450/380 ma 2, 3, 4 cmos standby supply current (device deselected, freq = 0, v dd = max, all inputs static at cmos levels) i sb2 e e 30 ma 5, 6 sleep mode supply current (device deselected, freq = max, v dd = max, all other inputs static at cmos levels, zz v dd 0.2 v) i zz e e 15 ma 1, 5, 6 ttl standby supply current (device deselected, freq = 0, v dd = max, all inputs static at ttl levels) i sb3 e e 35 ma 5, 7 clock running (device deselected, mcm63p737k / 819k166 freq = max, v dd = max, all inputs mcm63p737k / 819k150 toggling at cmos levels) mcm63p737k / 819k133 i sb4 e e 185/170 175/160 160/145 ma 5, 6 static clock running mcm63p737k / 819k166 (device deselected, mcm63p737k / 819k150 freq = max,v dd = max, all inputs mcm63p737k / 819k133 static at ttl levels) i sb5 e e 75/65 70/60 65/55 ma 5, 7 notes: 1. lbo and zz pins have an internal pullup and pulldown, respectively; and will exhibit leakage currents of 5 m a. 2. reference ac operating conditions and characteristics for input and timing. 3. all addresses transition simultaneously low (lsb) then high (msb). 4. data states are all zero. 5. device is deselected as defined by the truth table. 6. cmos levels for i/os are v it v ss + 0.2 v or v ddq 0.2 v. cmos levels for other inputs are v in v ss + 0.2 v or v dd 0.2 v. 7. ttl levels for i/os are v it v il or v ih2 . ttl levels for other inputs are v in v il or v ih. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mcm63p737k ? mcm63p819k 12 motorola fast sram capacitance (f = 1.0 mhz, t a = 0 to 70 c, periodically sampled rather than 100% tested) parameter symbol min typ max unit input capacitance c in e 4 5 pf input/output capacitance c i/o e 7 8 pf ac operating conditions and characteristics (v dd = 3.3 v +10%, 5%, t a = 0 to 70 c, unless otherwise noted) input timing measurement reference level 1.5 v . . . . . . . . . . . . . . . input pulse levels 0 to 3.0 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input rise/fall time 1.0 v/ns (20% to 80%) . . . . . . . . . . . . . . . . . . . . output timing reference level 1.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . output load see figure 2 unless otherwise noted . . . . . . . . . . . . . . read/write cycle timing (see notes 1 and 2) mcm63p737k166 mcm63p819k166 mcm63p737k150 mcm63p819k150 mcm63p737k133 mcm63p819k133 parameter symbol min max min max min max unit notes cycle time t khkh 6 e 6.7 e 7.5 e ns clock high pulse width t khkl 2.4 e 2.6 e 3 e ns 3 clock low pulse width t klkh 2.4 e 2.6 e 3 e ns 3 clock access time t khqv e 3.5 e 3.8 e 4 ns output enable to output valid t glqv e 3.5 e 3.5 e 3.8 ns clock high to output active t khqx1 0 e 0 e 0 e ns 4, 5 clock high to output change t khqx2 1.5 e 1.5 e 1.5 e ns 4 output enable to output active t glqx 0 e 0 e 0 e ns 4, 5 output disable to q highz t ghqz e 3.5 e 3.5 e 3.8 ns 4, 5 clock high to q highz t khqz 1.5 3.5 1.5 3.5 1.5 3.5 ns 4, 5 setup times: address adsp , adsc , adv data in write chip enable t adkh t adskh t dvkh t wvkh t evkh 1.5 e 1.5 e 1.5 e ns hold times: address adsp , adsc , adv data in write chip enable t khax t khadsx t khdx t khwx t khex 0.5 e 0.5 e 0.5 e ns notes: 1. write is defined as either any sbx and sw low or sgw is low. chip enable is defined as se1 low, se2 high, and se3 low whenever adsp or adsc is asserted. 2. all read and write cycle timings are referenced from k or g . 3. in order to reduce test correlation issues and to reduce the effects of application specific input edge rate variations on co rrelation between data sheet parameters and actual system performance, fsram ac parametric specifications are always specified at v ddq /2. in some design exercises, it is desirable to evaluate timing using other reference levels. since the maximum test input edge rate is kn own and is given in the ac test conditions section of the data sheet as 1 v/ns, one can easily interpolate timing values to other referenc e levels. 4. this parameter is sampled and not 100% tested. 5. measured at 200 mv from steady state. output z 0 = 50 w r l = 50 w 1.5 v figure 1. ac test load f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mcm63p737k ? mcm63p819k 13 motorola fast sram figure 2. lumped capacitive load and typical derating curve 2000 1600 1200 800 400 0 lumped capacitance, c l (pf) 100 80 60 40 20 0 c l clock access time delay (ps) output 2400 200 600 1800 1400 1000 2200 2.4 input waveform t r test point output buffer 2.4 0.6 0.6 output waveform output load t f unloaded rise and fall time measurement notes: 1. input waveform has a slew rate of 1 v/ns. 2. rise time is measured from 0.6 to 2.4 v unloaded. 3. fall time is measured from 2.4 to 0.6 v unloaded. figure 3. unloaded rise and fall time characterization 2.4 2.4 0.6 0.6 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mcm63p737k ? mcm63p819k 14 motorola fast sram burst read single read adsc t khkl t khkh dqx e k adsp adv q(a) q(n) burst write adsp, sa sa ab read/write cycles t klkh cd se1 w q(b) q(b+1) t khqv burst wraps around q(b+2) q(b+3) q(b) d(c) d(c+1) d(c+2) d(c+3) q(d) t glqv deselected single read se2, se3 ignored g t khqz t khqx1 t khqx2 t ghqz t glqx note: e low = se2 high and se3 low. w low = sgw low and/or sw and sbx low. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
zz e k ads adv sleep mode timing w g t zzqz ads high = both adsc, adsp high. note: ads low = adsc low or adsp low. t zzs t zzrec e low = se1 low, se2 high, se3 low. addr dq normal operation no reads or writes allowed in sleep mode no new reads or writes allowed normal operation i zz i (max) specifications will not be met if inputs toggle. zz i dd mcm63p737k ? mcm63p819k 15 motorola fast sram f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mcm63p737k ? mcm63p819k 16 motorola fast sram application information sleep mode a sleep mode feature, the zz pin, has been implemented on the mcm63p737k and mcm63p819k. it allows the sys- tem designer to place the ram in the lowest possible power condition by asserting zz. the sleep mode timing diagram shows the different modes of operation: normal operation, no read/write allowed, and sleep mode. each mode has its own set of constraints and conditions that are allowed. normal operation: all inputs must meet setup and hold times prior to sleep and t zzrec nanoseconds after re- covering from sleep. clock (k) must also meet cycle, high, and low times during these periods. two cycles prior to sleep, initiation of either a read or write operation is not allowed. no read/write: during the period of time just prior to sleep and during recovery from sleep, the assertion of either adsc , adsp , or any write signal is not allowed. if a write operation occurs during these periods, the memory array may be corrupted. validity of data out from the ram can not be guaranteed immediately after zz is asserted (prior to being in sleep). sleep mode: the ram automatically deselects itself. the ram disconnects its internal clock buffer. the external clock may continue to run without impacting the rams sleep current (i zz ). all inputs are allowed to toggle e the ram will not be selected and perform any reads or writes. however, if inputs toggle, the i zz (max) specification will not be met. note: it is invalid to go from stop clock mode directly into sleep mode. nonburst synchronous operation although this burstram has been designed for high end mpubased systems, these srams can be used in other high speed memory applications that do not require the burst address feature. most l2 caches designed with a synchro- nous interface can make use of the mcm63p737k and mcm63p819k. the burst counter feature of the burstrams can be disabled, and the srams can be configured to act upon a continuous stream of addresses. see figure 5. control pin tie values example (h v ih , l v il ) nonburst adsp adsc adv se1 se2 lbo sync nonburst, pipelined sram h l h l h x note: alt hough x is specified in the table as a don't care, the pin must be tied either high or low. writes reads dq k q(b) q(a) addr a b cd ef gh w q(d) q(c) d(f) d(e) d(h) d(g) g figure 4. example configuration as nonburst synchronous sram se3 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mcm63p737k ? mcm63p819k 17 motorola fast sram mcm 63p819k xx x x motorola memory prefix part number full part numbers e mcm63p737ktq166 mcm63p737ktq150 mcm63p737ktq133 mcm63p737ktq166r mcm63p737ktq150r mcm63p737ktq133r mcm63p737kzp166 mcm63p737kzp150 mcm63p737kzp133 mcm63p737kzp166r mcm63p737kzp150r mcm63p737kzp133r mcm63p819ktq166 mcm63p819ktq150 mcm63p819ktq133 mcm63p819ktq166r mcm63p819ktq150r mcm63p819ktq133r mcm63p819kzp166 MCM63P819KZP150 mcm63p819kzp133 mcm63p819kzp166r MCM63P819KZP150r mcm63p819kzp133r package (tq = tqfp, zp = pbga) blank = trays, r = tape and reel speed (166 = 166 mhz, 150 = 150 mhz, 133 = 133 mhz) ordering information (order by full part number) 63p737k f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mcm63p737k ? mcm63p819k 18 motorola fast sram tq package tqfp case 983a01 dim min max min max inches millimeters a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.45 0.053 0.057 b 0.22 0.38 0.009 0.015 b1 0.22 0.33 0.009 0.013 c 0.09 0.20 0.004 0.008 c1 0.09 0.16 0.004 0.006 d 22.00 bsc 0.866 bsc e 16.00 bsc 0.630 bsc e1 14.00 bsc 0.551 bsc e 0.65 bsc 0.026 bsc l 0.45 0.75 0.018 0.030 l1 1.00 ref 0.039 ref l2 0.50 ref s 0.20 0.008 r1 0.08 0.003 r2 0.08 0.20 0.003 0.008 0 7 0 7 0 0 11 13 11 13 11 13 11 13 1 2 3 d1 20.00 bsc 0.787 bsc 0.020 ref notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane h is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums a, b and d to be determined at datum plane h. 5. dimensions d and e to be determined at seating plane c. 6. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 (0.010) per side. dimensions d1 and b1 do include mold mismatch and are determined at datum plane h. 7. dimension b does not include dambar protrusion. dambar protrusion shall not cause the b dimension to exceed 0.45 (0.018). ab 0.20 (0.008) h e d ab 0.20 (0.008) c d ab 0.20 (0.008) c d 0.10 (0.004) c 0.25 (0.010) s 0.05 (0.002) s ab m 0.13 (0.005) d s c e/2 d/2 e e1 d1 d d1/2 e1/2 e/2 4x 2x 30 tips 2x 20 tips d b a c h 1 3 2 100 81 80 51 50 31 30 1 plating section bb c1 c b b1 ???? ???? base metal a seating plane view ab s view ab a2 a1 r1 l2 l l1 r2 gage plane x view y b b x=a, b, or d package dimensions f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mcm63p737k ? mcm63p819k 19 motorola fast sram a b c d e f g h j k l m n p r t u d2 e2 4x 16x 119x top view bottom view side view d 0.20 6x e e 7654321 b 0.35 a c e 0.25 a 0.20 a a seating plane a a1 a2 a3 m 0.3 c a b m 0.15 a d1 e1 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. all dimensions in millimeters. 3. dimension b is the maximum solder ball diameter measured parallel to datum a. 4. datum a, the seating plane, is defined by the spherical crowns of the solder balls. dim min max millimeters a 2.40 a1 0.50 0.70 a2 1.30 1.70 a3 0.80 1.00 d 22.00 bsc d1 20.32 bsc d2 19.40 19.60 e 14.00 bsc e1 7.62 bsc e2 11.90 12.10 b 0.60 0.90 e 1.27 bsc b zp package 7 x 17 bump pbga case 99902 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mcm63p737k ? mcm63p819k 20 motorola fast sram motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, represe ntation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the applicati on or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. atypicalo para meters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all ope rating parameters, including atypicalso must be validated for each customer application by customer's technical experts. motorola does not convey any license under it s patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical imp lant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product cou ld create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expens es, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motoro la, inc. motorola, inc. is an equal opportunity/affirmative action employer. mfax is a trademark of motorola, inc. how to reach us: usa / europe / locations not listed: motorola literature distribution; japan : motorola japan ltd.; sps, technical information center, p.o. box 5405, denver, colorado, 80217. 1-303-675-2140 or 1-800-441-2447 3201, minamiazabu. minatoku, tokyo 1068573 japan. 81334403569 mfax ? : rmfax0@email.sps.mot.com t ouchtone 1-602-244-6609 asia / pacific: motorola semiconductors h.k. ltd.; silicon harbour centre, motorola fax back system us & c anada only 1-800-774-1848 2 dai king street, tai po industrial estate, tao po, n.t., hong kong. http ://sps.motorola.com /mfax / 852-26668334 home page : http ://motorola.com/sps / customer focus center: 1-800-521-6274 mcm63p737k/d ? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .

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